module fulladder_4bit_tb; 
 
    reg [3:0] a, b;          // 4-bit inputs 
    reg cin;                 // Carry-in 
    wire [3:0] sum;          // 4-bit sum output 
    wire carry;              // Carry-out 
 
    wire [4:0] exp_value;    // Expected value (4-bit sum + carry-out) 
 
    // Instantiate the 4-bit full adder 
    fulladder DUT ( 
        .a(a), 
        .b(b), 
        .cin(cin), 
        .sum(sum), 
        .carry(carry) 
    ); 
 
    initial begin 
        // Test all combinations of a, b, and cin 
        a = 4'b0000; b = 4'b0000; cin = 0; #10; 
        a = 4'b0001; b = 4'b0001; cin = 0; #10; 
        a = 4'b0010; b = 4'b0010; cin = 0; #10; 
        a = 4'b0011; b = 4'b0011; cin = 0; #10; 
        a = 4'b0100; b = 4'b0100; cin = 1; #10; 
        a = 4'b0101; b = 4'b0101; cin = 1; #10; 
        a = 4'b0110; b = 4'b0110; cin = 1; #10; 
        a = 4'b0111; b = 4'b0111; cin = 1; #10; 
        a = 4'b1000; b = 4'b1000; cin = 0; #10; 
        a = 4'b1111; b = 4'b1111; cin = 1; #10; 
        $strobe($time, ": Simulation ended with a=%b b=%b cin=%b", a, b, 
cin); 
        $finish; 
    end 
 
    // Checker logic 
    assign exp_value = a + b + cin; // Create golden output for comparison 
 
    initial begin 
        forever @ (*) begin 
         
            if (exp_value == {carry, sum}) begin 
                $display($time, ": Test Passed a=%b b=%b cin=%b | 
Expected=%b | Carry_actual=%b, Sum_actual=%b", 
                         a, b, cin, exp_value, carry, sum); 
            end else begin 
                $display($time, ": Test FAILED!!! a=%b b=%b cin=%b | 
Expected=%b | Carry_actual=%b, Sum_actual=%b", 
                         a, b, cin, exp_value, carry, sum); 
            end 
        end 
    end 
 
endmodule