module d_flipflop_tb(); 
 
  reg clk,rst, D; 
  wire Q; 
  reg Q_ref; 
 
  D_flipflop DUT (.clk(clk), .rst(rst), .D(D), .Q(Q)); 
   
  initial begin  
   
  clk=1'b0; 
  forever #5 clk = ~clk; 
  end 
   
  task reset_check(); 
    begin     
      D=1; 
      rst=1;       
       
      if(Q===1'b0 || Q===1'bx) 
        $display($time,": RESET is Working Fine!"); 
      else 
    $display($time,": OOPS!! RESET FAILED D=%b, clk=%b, rst= %b, Q=%b, 
Q_ref=%b",D,clk,rst,Q,Q_ref);     
    end 
  endtask 
 
  initial begin 
 
  reset_check(); 
  #10; 
 
  rst=0; 
  #10; 
  D=1; 
  #10; 
   
  D=0; 
  #10; 
 
  rst=1; 
  #10; 
 
  D=0; 
  #10; 
 
  D=1; 
  #10; 
  $finish; 
  end 
 
  //Golden output / Dff behaviour 
  initial begin 
    forever @(posedge clk or posedge rst) 
    begin 
      if(rst) 
        Q_ref=1'b0; 
      else if(clk) 
        Q_ref = D; 
    end 
  end 
 
   
  //Comparison checker for golden and actual 
  always@(posedge clk or posedge rst) 
      begin 
      if(Q_ref !==1'bx) begin 
    if(Q_ref === Q) 
      $display($time,": Test PASSED D=%b, clk=%b, rst= %b, Q=%b, 
Q_ref=%b",D,clk,rst,Q,Q_ref); 
 
    else  
      $display($time,": OOPS!! Test FAILED D=%b, clk=%b, rst= %b, Q=%b, 
Q_ref=%b",D,clk,rst,Q,Q_ref); 
 
      end 
  end 
   
endmodule